Interactive CLI Commands Reference¶
This is an auto-generated reference of all FABulous CLI commands available in interactive mode.
User Design Flow¶
synthesis¶
Run Yosys synthesis for the specified Verilog files.
Performs FPGA synthesis using Yosys with the nextpnr JSON backend to synthesize Verilog designs and generate nextpnr-compatible JSON files for place and route. It supports various synthesis options including LUT architecture, FSM optimization, carry mapping, and different output formats.
Arguments:
Argument |
Type |
Required |
Default |
Description |
|---|---|---|---|---|
|
Path |
No |
- |
Path to the target files. |