port¶
Port definition module for FPGA fabric.
This module contains the Port class, which represents a connection point on a tile in the FPGA fabric. Ports define the physical and logical characteristics of wires entering or leaving a tile, including their direction, source and destination names, offsets, and wire counts. These definitions are typically parsed from a CSV file that describes the fabric architecture.
Classes¶
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Store all the port information defined in the CSV file. |
Module Contents¶
Port¶
- Port :module:
Store all the port information defined in the CSV file.
The name, inOut and sideOfTile are added attributes to aid the generation of the fabric.
The name and inOut are related. If the inOut is INPUT, then the name is the source name of the port on the tile. Otherwise, the name is the destination name of the port on the tile.
The sideOfTile defines where the port is physically located on the tile, since for a north direction wire, the input will be physically located on the south side of the tile. The sideOfTile will make determining where the port is located much easier.
- ivar wireDirection:
The direction attribute in the CSV file
- vartype wireDirection:
Direction
- ivar sourceName:
The source_name attribute in the CSV file
- vartype sourceName:
str
- ivar xOffset:
The X-offset attribute in the CSV file
- vartype xOffset:
int
- ivar yOffset:
The Y-offset attribute in the CSV file
- vartype yOffset:
int
- ivar destinationName:
The destination_name attribute in the CSV file
- vartype destinationName:
str
- ivar wireCount:
The wires attribute in the CSV file
- vartype wireCount:
int
- ivar name:
The name of the port
- vartype name:
str
- ivar inOut:
The IO direction of the port
- vartype inOut:
IO
- ivar sideOfTile:
The side on which the port is physically located in the tile
- vartype sideOfTile:
Side
- expandPortInfomode = 'SwitchMatrix' :module:
Expand the port information to the individual bit signal.
If ‘Indexed’ is in the mode, then brackets are added to the signal name.
- param mode:
Mode for expansion. Defaults to “SwitchMatrix”. Possible modes are ‘all’, ‘allIndexed’, ‘Top’, ‘TopIndexed’, ‘AutoTop’, ‘AutoTopIndexed’, ‘SwitchMatrix’, ‘SwitchMatrixIndexed’, ‘AutoSwitchMatrix’, ‘AutoSwitchMatrixIndexed’
- type mode:
str, optional
- returns:
A tuple of two lists. The first list contains the source names of the ports and the second list contains the destination names of the ports.
- rtype:
tuple[list[str], list[str]]
- expandPortInfoByNameindexed = False, prefix = '', escape = False :module:
Expand port information to individual wire names.
Generates a list of individual wire names for this port, accounting for wire count and offset calculations. For termination ports (NULL), the wire count is multiplied by the Manhattan distance.
- param indexed:
If True, wire names use bracket notation (e.g., port[0]). If False, wire names use simple concatenation (e.g., port0). Defaults to False.
- type indexed:
bool, optional
- param prefix:
A prefix to prepend to the port name, by default “”.
- type prefix:
str, optional
- param escape:
If True, escape special characters in the port names (e.g., for regex), by default False.
- type escape:
bool, optional
- returns:
List of individual wire names for this port.
- rtype:
list[str]
- expandPortInfoByNameTopindexed = False, prefix = '', escape = False :module:
Expand port information for top-level connections.
Similar to expandPortInfoByName but specifically for top-level tile connections. The start index is calculated differently to handle the top slice of wires for routing fabric connections.
- param indexed:
If True, wire names use bracket notation (e.g., port[0]). If False, wire names use simple concatenation (e.g., port0). Defaults to False.
- type indexed:
bool, optional
- param prefix:
A prefix to prepend to the port name, by default “”.
- type prefix:
str, optional
- param escape:
If True, escape special characters in the port names (e.g., for regex), by default False.
- type escape:
bool, optional
- returns:
List of individual wire names for top-level connections.
- rtype:
list[str]
- getPortRegexindexed = False, prefix = '' :module:
Expand port information to individual wire names.
Generates a regex expression for this port, accounting for wire count and offset calculations.
- param indexed:
If True, wire names use bracket notation (e.g., port[0]). If False, wire names use simple concatenation (e.g., port0). Defaults to False.
- type indexed:
bool, optional
- param prefix:
A prefix to prepend to the port name, by default “”.
- type prefix:
str, optional
- returns:
A regex expression matching the port’s wire names.
- rtype:
str