bel¶
Basic Element of Logic (BEL) definition module.
This module contains the Bel class which represents a Basic Element of Logic in the FPGA fabric. BELs are the fundamental building blocks that can be placed and configured within tiles, such as LUTs, flip-flops, and other logic elements.
Classes¶
|
Information about a single BEL. |
Module Contents¶
Bel¶
- Bel(src, prefix, module_name, internal, external, configPort, sharedPort, configBit, belMap, userCLK, ports_vectors, carry, localShared) :module:
Information about a single BEL.
The information is parsed from the directory of the BEL in the CSV definition file. There are some things to be noted:
The parsed name will contain the prefix of the bel.
The sharedPort attribute is a list of Tuples with the name of the port and IO information, which is not expanded out yet.
If a port is marked as both shared and external, the port is considered as shared, as a result, signals like UserCLK will be in the shared port list, but not in the external port list.
- param src:
The source directory path of the BEL.
- type src:
Path
- param prefix:
The prefix of the BEL.
- type prefix:
str
- param module_name:
The name of the module in the BEL.
- type module_name:
str
- param internal:
List of internal ports with their IO direction.
- type internal:
list[tuple[str, IO]]
- param external:
List of external ports with their IO direction.
- type external:
list[tuple[str, IO]]
- param configPort:
List of configuration ports with their IO direction.
- type configPort:
list[tuple[str, IO]]
- param sharedPort:
List of shared ports with their IO direction.
- type sharedPort:
list[tuple[str, IO]]
- param configBit:
The number of configuration bits of the BEL.
- type configBit:
int
- param belMap:
The feature map of the BEL.
- type belMap:
dict[str, dict]
- param userCLK:
Whether the BEL has userCLK port.
- type userCLK:
bool
- param ports_vectors:
Dictionary structure to save vectorized port information.
- type ports_vectors:
dict[str, dict[str, tuple[IO, int]]]
- param carry:
Carry chains by name.
- type carry:
dict[str, dict[IO, str]]
- param localShared:
Local shared ports of the BEL.
- type localShared:
dict[str, tuple[str, IO]]
- ivar src:
The source directory of the BEL given in the CSV file.
- vartype src:
Path
- ivar prefix:
The prefix of the BEL given in the CSV file.
- vartype prefix:
str
- ivar name:
The name of the BEL, extracted from the source directory.
- vartype name:
str
- ivar module_name:
The name of the module in the bel. For verlog we can extract this from the RTL. For VHDL this is currently the same as name.
- vartype module_name:
str
- ivar filetype:
The file type of the BEL.
- vartype filetype:
HDLType
- ivar inputs:
All the normal input ports of the BEL.
- vartype inputs:
list[str]
- ivar outputs:
All the normal output ports of the BEL.
- vartype outputs:
list[str]
- ivar externalInput:
All the external input ports of the BEL.
- vartype externalInput:
list[str]
- ivar externalOutput:
All the external output ports of the BEL.
- vartype externalOutput:
list[str]
- ivar configPort:
All the config ports of the BEL.
- vartype configPort:
list[tuple[str, IO]]
- ivar sharedPort:
All the shared ports of the BEL.
- vartype sharedPort:
list[tuple[str, IO]]
- ivar configBit:
The number of config bits of the BEL.
- vartype configBit:
int
- ivar language:
Language of the BEL. Currently only VHDL and Verilog are supported.
- vartype language:
str
- ivar belFeatureMap:
The feature map of the BEL.
- vartype belFeatureMap:
dict[str, dict]
- ivar withUserCLK:
Whether the BEL has userCLK port. Default is False.
- vartype withUserCLK:
bool
- ivar ports_vectors:
Dict structure to save vectorized port information {<porttype>:{<portname>:(IO, <portwidth>)}}
- vartype ports_vectors:
dict[str, dict[str, tuple[IO, int]]]
- ivar carry:
Carry chains by name. carry_name : {direction : port_name}
- vartype carry:
dict[str, dict[IO, str]]
- ivar localShared:
{RESET/ENABLE,(portname, IO)} Local shared ports of the BEL. Are only shared in the Tile, not in the fabric.
- vartype localShared:
dict[str,tuple[str, IO]]
- raises ValueError:
If the file type is not recognized (not .sv, .v, .vhd, or .vhdl).