gen_design_top_wrapper

User design top wrapper generation module.

This module provides functionality to generate top-level wrappers for user designs that interface with the FPGA fabric. The wrapper handles signal mapping between user logic and fabric I/O ports.

Functions

generateUserDesignTopWrapper(fabric, user_design_path, ...)

Generate a top wrapper for the user design.

Module Contents

generateUserDesignTopWrapper(fabric, user_design_path, output)[source]

Generate a top wrapper for the user design.

This function creates a Verilog top-level wrapper that instantiates the user’s design and connects its ports to the fabric’s external I/O BELs. It automatically discovers external ports from the fabric definition and generates the necessary wiring and BEL instantiations.

Parameters:

  • fabric (Fabric) – Fabric object

  • user_design_path (Path) – Path to the user design file

  • output (Path) – Path to output the user design top wrapper

Raises:

  • InvalidFileType – Output file is not a Verilog file or user design path is not a file

  • FileNotFoundError – User design file is not a file or does not exist

Return type:

None