tile_geometry

Tile geometry generation and management for FABulous FPGA tiles.

This module provides the TileGeometry class for representing and generating the geometric layout of FPGA tiles, including switch matrices, BELs, and interconnect wires. It handles both direct connections to neighboring tiles and complex stair-like routing for longer-distance connections.

Classes

TileGeometry

A data structure representing the geometry of a tile.

Module Contents

TileGeometry

TileGeometry   :module:

A data structure representing the geometry of a tile.

Initializes all attributes to default values: empty name, zero dimensions, no border, and empty lists for geometric components.

ivar name:

Name of the tile

vartype name:

str

ivar width:

Width of the tile

vartype width:

int

ivar height:

Height of the tile

vartype height:

int

ivar border:

Border of the fabric the tile is on

vartype border:

Border

ivar wireConstraints:

Wire constraints of the tile

vartype wireConstraints:

WireConstraints

ivar neighbourConstraints:

Wire constraints of neighbouring tiles

vartype neighbourConstraints:

WireConstraints | None

ivar smGeometry:

Geometry of the tiles switch matrix

vartype smGeometry:

SmGeometry

ivar belGeomList:

List of the geometries of the tiles bels

vartype belGeomList:

list[BelGeometry]

ivar wireGeomList:

List of the geometries of the tiles wires

vartype wireGeomList:

list[WireGeometry]

ivar stairWiresList:

List of the stair-like wires of the tile

vartype stairWiresList:

list[StairWires]

ivar stairWireOffset:

Offset for stair wires, relative to regular wires Should be relatively small, to prevent generating stair wires overlapping with regular wires.

vartype stairWireOffset:

int

ivar currPortGroupId:

Current port group ID being processed

vartype currPortGroupId:

int

ivar queuedAdjustmentBottom:

Queued adjustment for bottom positioning

vartype queuedAdjustmentBottom:

int

ivar queuedAdjustmentLeft:

Queued adjustment for left positioning

vartype queuedAdjustmentLeft:

int

ivar reserveStairSpaceBottom:

Whether to reserve space at bottom for stair wires

vartype reserveStairSpaceBottom:

bool

ivar reserveStairSpaceLeft:

Whether to reserve space at left for stair wires

vartype reserveStairSpaceLeft:

bool

ivar eastMiddleY:

Middle Y coordinate for east side

vartype eastMiddleY:

int

ivar northMiddleX:

Middle X coordinate for north side

vartype northMiddleX:

int

ivar southMiddleX:

Middle X coordinate for south side

vartype southMiddleX:

int

ivar westMiddleY:

Middle Y coordinate for west side

vartype westMiddleY:

int

adjustDimensionsmaxWidthInColumn, maxHeightInRow, maxSmWidthInColumn, maxSmRelXInColumn      :module:

Adjust tile dimensions to match maximum values in fabric grid.

Normalizes the tile dimensions and switch matrix positioning to align with the maximum dimensions found in the same fabric column/row, ensuring uniform tile sizing across the fabric.

param maxWidthInColumn:

Maximum width among tiles in the same column

type maxWidthInColumn:

int

param maxHeightInRow:

Maximum height among tiles in the same row

type maxHeightInRow:

int

param maxSmWidthInColumn:

Maximum switch matrix width in the same column

type maxSmWidthInColumn:

int

param maxSmRelXInColumn:

Maximum switch matrix relative X position in the same column

type maxSmRelXInColumn:

int

adjustSmPoslowestSmYInRow, padding      :module:

Ajusts the position of the switch matrix.

This is done by using the lowest Y coordinate of any switch matrix in the same row for reference.

After this step is completed for all switch matrices, their southern edge will be on the same Y coordinate, allowing for easier inter-tile routing.

generateBelWires      :module:

Generate the wires between the switch matrix and its bels.

generateDirectWirespadding      :module:

Generate wires to neighbouring tiles, which are straightforward to generate.

param padding:

The padding value to use for wire generation

type padding:

int

raises InvalidPortType:

If a port with offset 1 has no tile side defined

generateGeometrytile, padding      :module:

Generate the geometry for a tile.

Creates geometric representations for all BELs and the switch matrix, then calculates the overall tile dimensions based on the generated components and padding requirements.

param tile:

The Tile object to generate geometry for

type tile:

Tile

param padding:

The padding space to add around components

type padding:

int

generateIndirectWires      :module:

Generate wires to non-neighbouring tiles.

These wires require staircase-like routing patterns to reach tiles that are not direct neighbors (offset >= 2). The routing varies by tile side and wire direction.

raises InvalidPortType:

If a port has abs(offset) > 1 but no tile side assigned.

generateWirespadding      :module:

Generate all wire geometries for the tile.

Creates wire geometries for BEL connections, direct connections to neighboring tiles, and indirect connections requiring stair-like routing. Ensures proper alignment of wire positions across different tile types.

param padding:

The padding space to add around wire routing

type padding:

int

indirectEastSideWireportGeom      :module:

Generate indirect wires on the east side of the tile with stair-like routing.

Creates staircase-shaped wire routing for connections that span multiple tiles eastward. Manages stair wire generation and space reservation based on wire direction and grouping.

param portGeom:

The port geometry defining the wire characteristics

type portGeom:

PortGeometry

indirectNorthSideWireportGeom      :module:

Generate indirect wires with stair-like routing.

Creates staircase-shaped wire routing for connections that span multiple tiles northward. Manages stair wire generation and space reservation based on wire direction and grouping.

param portGeom:

The port geometry defining the wire characteristics

type portGeom:

PortGeometry

indirectSouthSideWireportGeom      :module:

Generate indirect wires on the south side without creating stair-like wires.

Creates L-shaped wire routing for southward connections. Unlike north side wires, this method only generates the connection wires and reserves space for stair wires created by the north side method.

param portGeom:

The port geometry defining the wire characteristics

type portGeom:

PortGeometry

indirectWestSideWireportGeom      :module:

Generate indirect wires on the west side without creating stair-like wires.

Creates L-shaped wire routing for westward connections. Unlike east side wires, this method only generates the connection wires and reserves space for stair wires created by the east side method.

param portGeom:

The port geometry defining the wire characteristics

type portGeom:

PortGeometry

saveToCSVwriter      :module:

Save tile geometry data to CSV format.

Writes the tile geometry information including dimensions and all geometric components (switch matrix, BELs, wires, stair wires) to a CSV file using the provided writer.

param writer:

The CSV writer object to use for output

type writer:

csvWriter

setBelPositionspadding      :module:

Set BEL positions.

totalWireLines      :module:

Return the total amount of lines (segments) of wires of the tiles routing.