cmd_synthesis

Synthesis command implementation for the FABulous CLI.

This module provides the synthesis command functionality for the FABulous command-line interface. It implements Yosys-based FPGA synthesis targeting the nextpnr place-and- route tool, with support for various synthesis options and output formats.

The synthesis flow includes multiple stages, from reading the Verilog files through final netlist generation, with options for LUT mapping, FSM optimization, carry chain mapping, and memory inference.

Attributes

CMD_USER_DESIGN_FLOW
HELP
synthesis_parser

Functions

do_synthesis(self, args)

Run Yosys synthesis for the specified Verilog files.

Module Contents

CMD_USER_DESIGN_FLOW = 'User Design Flow'

HELP = Multiline-String

Show Value

"""
Runs Yosys using the Nextpnr JSON backend to synthesise the Verilog design
specified by <files> and generates a Nextpnr-compatible JSON file for the
further place and route process. By default the name of the JSON file generated
will be <first_file_provided_stem>.json.

Also logs usage errors or synthesis failures.

The following commands are executed by when executing the synthesis command:
    read_verilog <"projectDir"/user_design/top_wrapper.v>
    read_verilog <file>                 (for each file in files)
    read_verilog  -lib +/fabulous/prims.v
    read_verilog -lib <extra_plib.v>    (for each -extra-plib)

    begin:
        hierarchy -check
        proc

    flatten:    (unless -noflatten)
        flatten
        tribuf -logic
        deminout

    coarse:
        tribuf -logic
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm          (unless -nofsm)
        opt
        wreduce
        peepopt
        opt_clean
        techmap -map +/cmp2lut.v -map +/cmp2lcu.v     (if -lut)
        alumacc      (unless -noalumacc)
        share        (unless -noshare)
        opt
        memory -nomap
        opt_clean

    map_ram:    (unless -noregfile)
        memory_libmap -lib +/fabulous/ram_regfile.txt
        techmap -map +/fabulous/regfile_map.v

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine

    map_gates:
        opt -full
        techmap -map +/techmap.v -map +/fabulous/arith_map.v -D ARITH_<carry>
        opt -fast

    map_iopad:    (if -iopad)
        opt -full
        iopadmap -bits -outpad $__FABULOUS_OBUF I:PAD -inpad $__FABULOUS_IBUF O:PAD
            -toutpad IO_1_bidirectional_frame_config_pass ~T:I:PAD
            -tinoutpad IO_1_bidirectional_frame_config_pass ~T:O:I:PAD A:top
            (skip if '-noiopad')
        techmap -map +/fabulous/io_map.v

    map_ffs:
        dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x    without -complex-dff
        techmap -map +/fabulous/latches_map.v
        techmap -map +/fabulous/ff_map.v
        techmap -map <extra_map.v>...    (for each -extra-map)
        clean

    map_luts:
        abc -lut 4 -dress
        clean

    map_cells:
        techmap -D LUT_K=4 -map +/fabulous/cells_map.v
        clean

    check:
        hierarchy -check
        stat

    blif:
        opt_clean -purge
        write_blif -attr -cname -conn -param <file-name>

    json:
        write_json <file-name>
"""

do_synthesis(self, args)

Run Yosys synthesis for the specified Verilog files.

Performs FPGA synthesis using Yosys with the nextpnr JSON backend to synthesize Verilog designs and generate nextpnr-compatible JSON files for place and route. It supports various synthesis options including LUT architecture, FSM optimization, carry mapping, and different output formats.

Parameters:

• self (FABulous_CLI) – The CLI instance containing project and fabric information.

• args (Namespace) – Command arguments containing: - files: List of Verilog files to synthesize - top: Top module name (default: ‘top_wrapper’) - auto_top: Whether to automatically determine top module - json: Output JSON file path - blif: Output BLIF file path (optional) - edif: Output EDIF file path (optional) - lut: LUT architecture size (default: 4) - And various other synthesis options

Return type:

None

Notes

The synthesis process includes multiple stages: hierarchy checking, flattening, coarse synthesis, RAM mapping, gate mapping, FF mapping, LUT mapping, and final netlist generation. See the module docstring for detailed synthesis flow information.

synthesis_parser