Using the eFPGA

This contains information on how to run and configure the RTL-to-bitstream flow for a FABulous fabric. It mainly consists of the steps place and route, synthesis and building he actual binary bitstream from a FASM file.

• Synthesis
  • Yosys models
  • Yosys compilation
    • Building
    • User guide
      • CLI Synthesis
      • Manual Synthesis
• Place and Route
  • Nextpnr models
    • arch.cc
    • cells.cc
  • Nextpnr compilation
    • Building
    • User guide
    • Primitive instantiation
    • Constraints for the placement of IO/BELs
• FASM to Bitstream
  • User guide
    • Generating a bitstream using the CLI
    • Manually generating a bitstream
    • Example
  • Changing or adding new primitives