supertile¶
Supertile definition for FPGA fabric.
This module contains the SuperTile class, which represents a composite tile made up of multiple smaller, individual tiles. Supertiles allow for the creation of more larger, complex and hierarchical structures within the FPGA fabric, combining different functionalities into a single, reusable block.
Classes¶
|
Store the information about a super tile. |
Module Contents¶
SuperTile¶
- SuperTile :module:
Store the information about a super tile.
- ivar name:
The name of the super tile.
- vartype name:
str
- ivar tileDir:
Path to the tile directory.
- vartype tileDir:
Path
- ivar tiles:
The list of tiles that make up the super tile.
- vartype tiles:
list[Tile]
- ivar tileMap:
The map of the tiles that make up the super tile
- vartype tileMap:
list[list[Tile]]
- ivar bels:
The list of bels of that the super tile contains
- vartype bels:
list[Bel]
- ivar withUserCLK:
Whether the super tile has a userCLK port. Default is False.
- vartype withUserCLK:
bool
- property max_height¶
- Return the maximum height of the supertile.
- property max_width¶
Return the maximum width of the supertile.
- getInternalConnections :module:
Return all the internal connections of the supertile.
- returns:
A list of tuples which contains the internal connected port and the x and y coordinate of the tile.
- rtype:
list[tuple[list[Port], int, int]]
- getPortsAroundTile :module:
Return all the ports that are around the supertile.
The dictionary key is the location of where the tile is located in the supertile map with the format of “X{x}Y{y}”, where x is the x coordinate of the tile and y is the y coordinate of the tile. The top left tile will have key “00”.
- returns:
The dictionary of the ports around the super tile.
- rtype:
dict[str, list[list[Port]]]
- get_min_die_areax_pitch, y_pitch, x_pin_thickness_mult, y_pin_thickness_mult, x_spacing, y_spacing :module:
Calculate minimum SuperTile dimensions based on IO pin density.
For this supertile, aggregates IO pins from all constituent tiles that appear on the outer edges and calculates the minimum physical width and height required.
- param x_pitch:
Horizontal pitch between tracks (DBU).
- type x_pitch:
Decimal
- param y_pitch:
Vertical pitch between tracks (DBU).
- type y_pitch:
Decimal
- param x_pin_thickness_mult:
Pin thickness multiplier in the horizontal direction.
- type x_pin_thickness_mult:
Decimal
- param y_pin_thickness_mult:
Pin thickness multiplier in the vertical direction.
- type y_pin_thickness_mult:
Decimal
- param x_spacing:
Pin spacing in the horizontal direction (DBU).
- type x_spacing:
Decimal
- param y_spacing:
Pin spacing in the vertical direction (DBU).
- type y_spacing:
Decimal
- returns:
(min_width, min_height) where: - min_width: minimum width needed for north/south edge IO pins - min_height: minimum height needed for west/east edge IO pins
- rtype:
tuple[Decimal, Decimal]
Notes
For supertiles, we aggregate IO pins from all constituent tiles that appear on the outer edges of the supertile to get conservative estimates for minimum dimensions.