tile

Tile class definition for FPGA fabric representation.

Classes

Tile	Store information about a tile.

Module Contents

Tile

Tile(name, ports, bels, tileDir, matrixDir, gen_ios, userCLK, configBit = 0, pinOrderConfig = None)   :module:

Store information about a tile.

param name:

The name of the tile

type name:

str

param ports:

List of ports for the tile

type ports:

list[Port]

param bels:

List of Basic Elements of Logic (BELs) in the tile

type bels:

list[Bel]

param tileDir:

Directory path for the tile

type tileDir:

Path

param matrixDir:

Directory path for the tile matrix

type matrixDir:

Path

param gen_ios:

List of general I/O components

type gen_ios:

list[Gen_IO]

param userCLK:

True if the tile uses a clk signal

type userCLK:

bool

param configBit:

Number of configuration bits for the switch matrix. Default is 0.

type configBit:

int, optional

param pinOrderConfig:

Configuration for pin ordering on each side of the tile. If None, defaults to BUS_MAJOR sorting on all sides.

type pinOrderConfig:

dict[Side, PinOrderConfig] | None, optional

ivar name:

The name of the tile

vartype name:

str

ivar portsInfo:

The list of ports of the tile

vartype portsInfo:

list[Port]

ivar bels:

The list of BELs of the tile

vartype bels:

list[Bel]

ivar matrixDir:

The directory of the tile matrix

vartype matrixDir:

Path

ivar matrixConfigBits:

The number of config bits the tile switch matrix has

vartype matrixConfigBits:

int

ivar gen_ios:

The list of GEN_IOs of the tile

vartype gen_ios:

list[Gen_IO]

ivar withUserCLK:

Whether the tile has a userCLK port. Default is False.

vartype withUserCLK:

bool

ivar wireList:

The list of wires of the tile

vartype wireList:

list[Wire]

ivar tileDir:

The path to the tile folder

vartype tileDir:

Path

ivar partOfSuperTile:

Whether the tile is part of a super tile. Default is False.

vartype partOfSuperTile:

bool, optional

ivar pinOrderConfig:

Configuration for pin ordering on each side of the tile.

vartype pinOrderConfig:

dict, optional

property globalConfigBits

Get the total number of global configuration bits.

Calculates the sum of switch matrix configuration bits and all BEL configuration bits.

returns:

Total number of global configuration bits for the tile.

rtype:

int

getEastPortsio      :module:

Get all ports with east wire direction filtered by I/O type.

param io:

The I/O direction to filter by (INPUT or OUTPUT).

type io:

IO

returns:

List of east-direction ports with specified I/O type, excluding NULL ports.

rtype:

list[Port]

getEastSidePorts      :module:

Get all ports physically located on the east side of the tile.

returns:

List of ports on the east side, excluding NULL ports.

rtype:

list[Port]

getNorthPortsio      :module:

Get all ports with north wire direction filtered by I/O type.

param io:

The I/O direction to filter by (INPUT or OUTPUT).

type io:

IO

returns:

List of north-direction ports with specified I/O type, excluding NULL ports.

rtype:

list[Port]

getNorthSidePorts      :module:

Get all ports physically located on the north side of the tile.

returns:

List of ports on the north side, excluding NULL ports.

rtype:

list[Port]

getSouthPortsio      :module:

Get all ports with south wire direction filtered by I/O type.

param io:

The I/O direction to filter by (INPUT or OUTPUT).

type io:

IO

returns:

List of south-direction ports with specified I/O type, excluding NULL ports.

rtype:

list[Port]

getSouthSidePorts      :module:

Get all ports physically located on the south side of the tile.

returns:

List of ports on the south side, excluding NULL ports.

rtype:

list[Port]

getTileInputNames      :module:

Get all input port destination names for the tile.

returns:

List of destination names for input ports, excluding NULL and JUMP direction ports.

rtype:

list[str]

getTileOutputNames      :module:

Get all output port source names for the tile.

returns:

List of source names for output ports, excluding NULL and JUMP direction ports.

rtype:

list[str]

getWestPortsio      :module:

Get all ports with west wire direction filtered by I/O type.

param io:

The I/O direction to filter by (INPUT or OUTPUT).

type io:

IO

returns:

List of west-direction ports with specified I/O type, excluding NULL ports.

rtype:

list[Port]

getWestSidePorts      :module:

Get all ports physically located on the west side of the tile.

returns:

List of ports on the west side, excluding NULL ports.

rtype:

list[Port]

get_min_die_areax_pitch, y_pitch, x_pin_thickness_mult, y_pin_thickness_mult, x_spacing, y_spacing, frame_data_width = 32, frame_strobe_width = 20      :module:

Calculate minimum tile dimensions based on IO pin density.

For this tile, calculates the minimum physical width and height required to accommodate all IO pins at the PDK’s track pitch.

param x_pitch:

Horizontal pitch between tracks (DBU).

type x_pitch:

Decimal

param y_pitch:

Vertical pitch between tracks (DBU).

type y_pitch:

Decimal

param x_pin_thickness_mult:

Pin thickness multiplier in the horizontal direction.

type x_pin_thickness_mult:

Decimal

param y_pin_thickness_mult:

Pin thickness multiplier in the vertical direction.

type y_pin_thickness_mult:

Decimal

param x_spacing:

Pin spacing in the horizontal direction (DBU).

type x_spacing:

Decimal

param y_spacing:

Pin spacing in the vertical direction (DBU).

type y_spacing:

Decimal

param frame_data_width:

Frame data width, by default 32.

type frame_data_width:

int, optional

param frame_strobe_width:

Frame strobe width, by default 20.

type frame_strobe_width:

int, optional

returns:

(min_width, min_height) where: - min_width: minimum width needed for north/south edge IO pins - min_height: minimum height needed for west/east edge IO pins

rtype:

tuple[Decimal, Decimal]

Notes

The minimum dimensions are calculated as: - min_width = max(north_pins, south_pins) * x_pitch - min_height = max(west_pins, east_pins) * y_pitch

These constraints prevent the NLP solver from suggesting dimensions that are physically impossible due to IO pin spacing requirements.

get_port_countside      :module:

Count total number of expanded ports on a given side of the tile.

param side:

The side of the tile to count ports for.

type side:

Side

returns:

Total number of expanded ports on the given side.

rtype:

int