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FABulous: an Embedded FPGA Framework and CAD Tools v2.0.0b5.dev38+g45ffbc8f0
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FABulous: an Embedded FPGA Framework and CAD Tools v2.0.0b5.dev38+g45ffbc8f0
  • Getting Started
    • Quick start
    • Installation Method
      • venv based setup
      • uv based setup
      • Install Required CAD tools
      • docker based setup
      • Nix-based Development Environment
  • User Guide
    • Building your eFPGA
      • Fabric definition
      • Building fabric
      • FABulous Fabric Automation
      • Convert your design into GDSII format
      • GDS Flow Configuration Variables
    • CLI Usage Guide
      • FABulous CLI — Features and Usage
      • Interactive CLI Commands Reference
      • FABulous Configuration Variables
    • Using the eFPGA
      • Synthesis
        • Yosys models
        • Yosys compilation
      • Place and Route
        • Nextpnr models
        • Nextpnr compilation
      • FASM to Bitstream
    • Simulation and emulation
      • Simulation setup
      • Emulation setup
  • Development
  • Chip Gallery
  • Team and Contact
  • Publications
  • API Reference
    • fabulous
      • custom_exception
      • fabric_cad
        • gen_bitstream_spec
        • gen_design_top_wrapper
        • gen_npnr_model
      • fabric_definition
        • bel
        • configmem
        • define
        • fabric
        • gen_io
        • port
        • supertile
        • tile
        • wire
        • yosys_obj
      • fabric_generator
        • code_generator
          • code_generator
          • code_generator_VHDL
          • code_generator_Verilog
        • gds_generator
          • flows
            • fabric_macro_flow
            • flow_define
            • full_fabric_flow
            • tile_macro_flow
          • gen_io_pin_config_yaml
          • helper
          • script
            • fabric_io_place
            • odb_power
            • odb_protocol
            • tile_io_place
          • steps
            • add_buffer
            • auto_diode
            • condition_magic_drc
            • custom_pdn
            • extract_pdk_info
            • fabric_IO_placement
            • global_tile_opitmisation
            • odb_connect_pdn
            • round_die_area
            • tile_IO_placement
            • tile_optimisation
            • while_step
        • gen_fabric
          • fabric_automation
          • gen_configmem
          • gen_fabric
          • gen_helper
          • gen_switchmatrix
          • gen_tile
          • gen_top_wrapper
        • parser
          • parse_configmem
          • parse_csv
          • parse_hdl
          • parse_switchmatrix
      • fabulous
      • fabulous_api
      • fabulous_cli
        • cmd_synthesis
        • fabulous_cli
        • helper
      • fabulous_settings
      • geometry_generator
        • bel_geometry
        • fabric_geometry
        • geometry_gen
        • geometry_obj
        • port_geometry
        • sm_geometry
        • tile_geometry
        • wire_geometry
      • processpool
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Chip Gallery¶

Chips eFPGA_RISCV_TSMC180: eFPGA (ver.1) with RISC-V core and 1K DPRAM FORTE-ENG1 eFPGA_STRIVE_sky130: 1440 LUT4s + 180 LUT5s + dual-port memories for RF and FIFOs https://github.com/FPGA-Research/eFPGA---RTL-to-GDS-with-SKY130 eFPGA_caravel_sky130: CLBs, DSPs, RegFiles, BBRAMs Google Shuttle - MPW-2 https://github.com/nguyendao-uom/eFPGA_v3_caravel eFPGA_caravel_sky130: CLBs, DSPs, RegFiles, BBRAMs with custom cells Google Shuttle - MPW-3 https://github.com/FPGA-Research/FABulous-Sky---a-heterogeneous-FPGA-fabric-in-Skywater130 eFPGA_RISCV_sky130: RISCV with eFPGA for tensorflow micro applications Google Shuttle - MPW-3 https://github.com/nguyendao-uom/fuserisc_ver2 ICESOC_caravel: Ibex-Crypto-eFPGA for cryptography Google Shuttle - MPW-4 https://github.com/nguyendao-uom/ICESOC Open_eFPGA: Full-opensource eFPGA with OpenLane and SKY130 Google Shuttle - MPW5 https://github.com/nguyendao-uom/open_eFPGA Open_ReRAM_eFPGA: Full-opensource Reram_based eFPGA SKY130 Google Shuttle - MPW4 https://github.com/nguyendao-uom/rram_testchip
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