yosys_obj¶
Object representation of the Yosys Json file.
Attributes¶
Classes¶
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Represents a cell instance in a Yosys module. |
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Root object representing a complete Yosys JSON file. |
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Represents memory block details in a Yosys module. |
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Represents a module in a Yosys design. |
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Represents net/wire details in a Yosys module. |
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Represents port details in a Yosys module. |
Module Contents¶
YosysCellDetails¶
- YosysCellDetails :module:
Represents a cell instance in a Yosys module.
Cells are instantiated components like logic gates, flip-flops, or user-defined modules.
- ivar hide_name:
Whether to hide the cell name in output (1=hide, 0=show).
- vartype hide_name:
Literal[1, 0]
- ivar type:
Cell type/primitive name (e.g., “AND”, “DFF”, custom module name).
- vartype type:
str
- ivar parameters:
Cell parameters as string key-value pairs.
- vartype parameters:
KeyValue
- ivar attributes:
Cell attributes including metadata and synthesis directives.
- vartype attributes:
KeyValue
- ivar connections:
Port connections mapping port names to bit vectors.
- vartype connections:
dict[str, BitVector]
- ivar port_directions:
Direction of each port. Default is empty dict.
- vartype port_directions:
dict[str, Literal[“input”, “output”, “inout”]], optional
- ivar model:
Associated model name. Default is “”.
- vartype model:
str, optional
YosysJson¶
- YosysJson(path) :module:
Root object representing a complete Yosys JSON file.
Load and parse a HDL file to a Yosys JSON object.
This class provides the main interface for loading and analyzing Yosys JSON netlists. It contains all modules in the design and provides utility methods for common netlist analysis tasks.
- param path:
Path to a HDL file.
- type path:
Path
- ivar srcPath:
Path to the source JSON file.
- vartype srcPath:
Path
- ivar creator:
Tool that created the JSON (usually “Yosys”).
- vartype creator:
str
- ivar modules:
Dictionary mapping module names to YosysModule objects.
- vartype modules:
dict[str, YosysModule]
- ivar models:
Dictionary of behavioral models (implementation-specific).
- vartype models:
dict
- raises FileNotFoundError:
If the JSON file doesn’t exist.
- raises InvalidFileType:
If the file type is not .vhd, .vhdl, .v, or .sv.
- raises RuntimeError:
If Yosys or GHDL fails to process the file.
- raises ValueError:
If there is a miss match in the VHDL entity and the Yosys top module.
- getNetPortSrcSinksnet :module:
Find the source and sink connections for a given net.
This method analyzes the netlist to determine what drives a net (source) and what it connects to (sinks).
- param net:
Net ID to analyze.
- type net:
int
- returns:
A tuple containing: - Source: (cell_name, port_name) tuple for the driving cell/port - Sinks: List of (cell_name, port_name) tuples for driven cells/ports
- rtype:
tuple[tuple[str, str], list[tuple[str, str]]]
- raises ValueError:
If net is not found or has multiple drivers.
Notes
If no driver is found, the source will be (“”, “z”) indicating a high-impedance or undriven net.
- getTopModule :module:
Find and return the top-level module in the design.
The top module is identified by having a “top” attribute. If no “top” module is found, falls back to the first module with a “blackbox” attribute (e.g. for BEL definitions that only contain a blackbox module).
- returns:
A tuple containing: - The name of the top-level module (str) - The YosysModule object for the top-level module
- rtype:
tuple[str, YosysModule]
- raises ValueError:
If no top or blackbox module is found in the design.
- isTopModuleNetnet :module:
Check if a net ID corresponds to a top-level module port.
- param net:
Net ID to check.
- type net:
int
- returns:
True if the net is connected to a top module port, False otherwise.
- rtype:
bool
YosysMemoryDetails¶
- YosysMemoryDetails :module:
Represents memory block details in a Yosys module.
Memory blocks are inferred or explicitly instantiated memory elements.
- ivar hide_name:
Whether to hide the memory name in output (1=hide, 0=show).
- vartype hide_name:
Literal[1, 0]
- ivar attributes:
Memory attributes and metadata.
- vartype attributes:
KeyValue
- ivar width:
Data width in bits.
- vartype width:
int
- ivar start_offset:
Starting address offset.
- vartype start_offset:
int
- ivar size:
Memory size (number of addressable locations).
- vartype size:
int
YosysModule¶
- YosysModule(*, attributes, parameter_default_values, ports, cells, memories, netnames) :module:
Represents a module in a Yosys design.
A module contains the structural description of a digital circuit including its interface (ports), internal components (cells), memory blocks, and interconnections (nets).
- param attributes:
Module attributes dictionary.
- type attributes:
KeyValue
- param parameter_default_values:
Parameter defaults dictionary.
- type parameter_default_values:
KeyValue
- param ports:
Ports dictionary (will be converted to YosysPortDetails objects).
- type ports:
dict[str, YosysPortDetails]
- param cells:
Cells dictionary (will be converted to YosysCellDetails objects).
- type cells:
dict[str, YosysCellDetails]
- param memories:
Memories dictionary (will be converted to YosysMemoryDetails objects).
- type memories:
dict[str, YosysMemoryDetails]
- param netnames:
Netnames dictionary (will be converted to YosysNetDetails objects).
- type netnames:
dict[str, YosysNetDetails]
- ivar attributes:
Module attributes and metadata (e.g., “top” for top module).
- vartype attributes:
KeyValue
- ivar parameter_default_values:
Default values for module parameters.
- vartype parameter_default_values:
KeyValue
- ivar ports:
Dictionary mapping port names to YosysPortDetails.
- vartype ports:
dict[str, YosysPortDetails]
- ivar cells:
Dictionary mapping cell names to YosysCellDetails.
- vartype cells:
dict[str, YosysCellDetails]
- ivar memories:
Dictionary mapping memory names to YosysMemoryDetails.
- vartype memories:
dict[str, YosysMemoryDetails]
- ivar netnames:
Dictionary mapping net names to YosysNetDetails.
- vartype netnames:
dict[str, YosysNetDetails]
YosysNetDetails¶
- YosysNetDetails :module:
Represents net/wire details in a Yosys module.
Nets are the connections between cells and ports in the design.
- ivar hide_name:
Whether to hide the net name in output (1=hide, 0=show).
- vartype hide_name:
Literal[1, 0]
- ivar bits:
Bit vector representing the net’s signals.
- vartype bits:
BitVector
- ivar attributes:
Net attributes including unused bit information.
- vartype attributes:
KeyValue
- ivar offset:
Bit offset for multi-bit nets.
- vartype offset:
int
- ivar upto:
Upper bound for bit ranges.
- vartype upto:
int
- ivar signed:
Whether the net is signed (0=unsigned, 1=signed).
- vartype signed:
int
YosysPortDetails¶
- YosysPortDetails :module:
Represents port details in a Yosys module.
- ivar direction:
Port direction.
- vartype direction:
Literal[“input”, “output”, “inout”]
- ivar bits:
Bit vector representing the port’s signals.
- vartype bits:
BitVector
- ivar offset:
Bit offset for multi-bit ports.
- vartype offset:
int
- ivar upto:
Upper bound for bit ranges.
- vartype upto:
int
- ivar signed:
Whether the port is signed (0=unsigned, 1=signed).
- vartype signed:
int