FABulous.fabric_definition.Yosys_obj

Object representation of the Yosys Json file.

Classes

class YosysCellDetails

Represents a cell instance in a Yosys module.

Cells are instantiated components like logic gates, flip-flops, or user-defined modules.

hide_name

Whether to hide the cell name in output (1=hide, 0=show).

Type:

Literal[1, 0]

type

Cell type/primitive name (e.g., “AND”, “DFF”, custom module name).

Type:

str

parameters

Cell parameters as string key-value pairs.

Type:

KeyValue

attributes

Cell attributes including metadata and synthesis directives.

Type:

KeyValue

connections

Port connections mapping port names to bit vectors.

Type:

dict[str, BitVector]

port_directions

Direction of each port. Default is empty dict.

Type:

dict[str, Literal[“input”, “output”, “inout”]], optional

model

Associated model name. Default is “”.

Type:

str, optional

class YosysJson(path)

Root object representing a complete Yosys JSON file.

Load and parse a HDL file to a Yosys JSON object.

This class provides the main interface for loading and analyzing Yosys JSON netlists. It contains all modules in the design and provides utility methods for common netlist analysis tasks.

Parameters:

path (Path) – Path to a HDL file.

srcPath

Path to the source JSON file.

Type:

Path

creator

Tool that created the JSON (usually “Yosys”).

Type:

str

modules

Dictionary mapping module names to YosysModule objects.

Type:

dict[str, YosysModule]

models

Dictionary of behavioral models (implementation-specific).

Type:

dict

Raises:

• FileNotFoundError – If the JSON file doesn’t exist.

• InvalidFileType – If the file type is not .vhd, .vhdl, .v, or .sv.

• RuntimeError – If Yosys or GHDL fails to process the file.

• ValueError – If there is a miss match in the VHDL entity and the Yosys top module.

Parameters:

path (Path)

Methods:

getNetPortSrcSinks(net)

Find the source and sink connections for a given net.

This method analyzes the netlist to determine what drives a net (source) and what it connects to (sinks).

Parameters:

net (int) – Net ID to analyze.

Returns:

A tuple containing: - Source: (cell_name, port_name) tuple for the driving cell/port - Sinks: List of (cell_name, port_name) tuples for driven cells/ports

Return type:

tuple[tuple[str, str], list[tuple[str, str]]]

Raises:

ValueError – If net is not found or has multiple drivers.

Notes

If no driver is found, the source will be (“”, “z”) indicating a high-impedance or undriven net.

getTopModule()

Find and return the top-level module in the design.

The top module is identified by having a “top” attribute.

Returns:

A tuple containing: - The name of the top-level module (str) - The YosysModule object for the top-level module

Return type:

tuple[str, YosysModule]

Raises:

ValueError – If no top module is found in the design.

isTopModuleNet(net)

Check if a net ID corresponds to a top-level module port.

Parameters:

net (int) – Net ID to check.

Returns:

True if the net is connected to a top module port, False otherwise.

Return type:

bool

class YosysMemoryDetails

Represents memory block details in a Yosys module.

Memory blocks are inferred or explicitly instantiated memory elements.

hide_name

Whether to hide the memory name in output (1=hide, 0=show).

Type:

Literal[1, 0]

attributes

Memory attributes and metadata.

Type:

KeyValue

width

Data width in bits.

Type:

int

start_offset

Starting address offset.

Type:

int

size

Memory size (number of addressable locations).

Type:

int

class YosysModule(*, attributes, parameter_default_values, ports, cells, memories, netnames)

Represents a module in a Yosys design.

A module contains the structural description of a digital circuit including its interface (ports), internal components (cells), memory blocks, and interconnections (nets).

Parameters:

• attributes (KeyValue) – Module attributes dictionary.

• parameter_default_values (KeyValue) – Parameter defaults dictionary.

• ports (dict[str, YosysPortDetails]) – Ports dictionary (will be converted to YosysPortDetails objects).

• cells (dict[str, YosysCellDetails]) – Cells dictionary (will be converted to YosysCellDetails objects).

• memories (dict[str, YosysMemoryDetails]) – Memories dictionary (will be converted to YosysMemoryDetails objects).

• netnames (dict[str, YosysNetDetails]) – Netnames dictionary (will be converted to YosysNetDetails objects).

attributes

Module attributes and metadata (e.g., “top” for top module).

Type:

KeyValue

parameter_default_values

Default values for module parameters.

Type:

KeyValue

ports

Dictionary mapping port names to YosysPortDetails.

Type:

dict[str, YosysPortDetails]

cells

Dictionary mapping cell names to YosysCellDetails.

Type:

dict[str, YosysCellDetails]

memories

Dictionary mapping memory names to YosysMemoryDetails.

Type:

dict[str, YosysMemoryDetails]

netnames

Dictionary mapping net names to YosysNetDetails.

Type:

dict[str, YosysNetDetails]

Methods:

class YosysNetDetails

Represents net/wire details in a Yosys module.

Nets are the connections between cells and ports in the design.

hide_name

Whether to hide the net name in output (1=hide, 0=show).

Type:

Literal[1, 0]

bits

Bit vector representing the net’s signals.

Type:

BitVector

attributes

Net attributes including unused bit information.

Type:

KeyValue

offset

Bit offset for multi-bit nets.

Type:

int

upto

Upper bound for bit ranges.

Type:

int

signed

Whether the net is signed (0=unsigned, 1=signed).

Type:

int

class YosysPortDetails

Represents port details in a Yosys module.

direction

Port direction.

Type:

Literal[“input”, “output”, “inout”]

bits

Bit vector representing the port’s signals.

Type:

BitVector

offset

Bit offset for multi-bit ports.

Type:

int

upto

Upper bound for bit ranges.

Type:

int

signed

Whether the port is signed (0=unsigned, 1=signed).

Type:

int

Functions

Module Attributes

BitVector

KeyValue