FABulous.fabric_definition.Yosys_obj#

Object representation of the Yosys Json file.

Classes#

class YosysCellDetails[source]#

Represents a cell instance in a Yosys module.

Cells are instantiated components like logic gates, flip-flops, or user-defined modules.

hide_name[source]#

Whether to hide the cell name in output (1=hide, 0=show).

Type:: {0, 1}

type[source]#

Cell type/primitive name (e.g., “AND”, “DFF”, custom module name).

Type:: str

parameters[source]#

Cell parameters as string key-value pairs.

Type:: dict[str, str]

attributes[source]#

Cell attributes including metadata and synthesis directives.

Type:: dict[str, str | int]

connections[source]#

Port connections mapping port names to bit vectors.

Type:: dict[str, BitVector]

port_directions[source]#

Direction of each port. Default is empty dict.

Type:: dict[str, {“input”, ”output”, ”inout”}], optional

model[source]#

Associated model name. Default is “”.

Type:: str, optional

class YosysJson(path)[source]#

Root object representing a complete Yosys JSON file.

This class provides the main interface for loading and analyzing Yosys JSON netlists. It contains all modules in the design and provides utility methods for common netlist analysis tasks.

Parameters:: path (Path)

srcPath[source]#

Path to the source JSON file.

Type:: Path

creator[source]#

Tool that created the JSON (usually “Yosys”).

Type:: str

modules[source]#

Dictionary mapping module names to YosysModule objects.

Type:: dict[str, YosysModule]

models[source]#

Dictionary of behavioral models (implementation-specific).

Type:: dict

Load and parse a HDL file to a Yosys JSON object.

Methods:

getNetPortSrcSinks(net)[source]#

Find the source and sink connections for a given net.

This method analyzes the netlist to determine what drives a net (source) and what it connects to (sinks).

Parameters:: net (int) – Net ID to analyze.
Returns:: A tuple containing: - Source: (cell_name, port_name) tuple for the driving cell/port - Sinks: List of (cell_name, port_name) tuples for driven cells/ports
Return type:: tuple[tuple[str, str], list[tuple[str, str]]]
Raises:: ValueError – If net is not found or has multiple drivers.

Notes

If no driver is found, the source will be (“”, “z”) indicating a high-impedance or undriven net.

getTopModule()[source]#

Find and return the top-level module in the design.

The top module is identified by having a “top” attribute.

Returns:: A tuple containing: - The name of the top-level module (str) - The YosysModule object for the top-level module
Return type:: tuple[str, YosysModule]
Raises:: ValueError – If no top module is found in the design.

isTopModuleNet(net)[source]#

Check if a net ID corresponds to a top-level module port.

Parameters:: net (int) – Net ID to check.
Returns:: True if the net is connected to a top module port, False otherwise.
Return type:: bool

class YosysMemoryDetails[source]#

Represents memory block details in a Yosys module.

Memory blocks are inferred or explicitly instantiated memory elements.

hide_name[source]#

Whether to hide the memory name in output (1=hide, 0=show).

Type:: {0, 1}

attributes[source]#

Memory attributes and metadata.

Type:: dict[str, str]

width[source]#

Data width in bits.

Type:: int

start_offset[source]#

Starting address offset.

Type:: int

size[source]#

Memory size (number of addressable locations).

Type:: int

class YosysModule(*, attributes, parameter_default_values, ports, cells, memories, netnames)[source]#

Represents a module in a Yosys design.

A module contains the structural description of a digital circuit including its interface (ports), internal components (cells), memory blocks, and interconnections (nets).

Parameters: