FABulous.fabric_generator.gen_fabric.gen_tile#

Tile generation module for FABulous FPGA architecture.

This module generates RTL code for individual tiles and super tiles within an FPGA fabric. It handles the integration of Basic Elements of Logic (BELs), switch matrices, and configuration infrastructure into complete tile implementations.

Key features: - Individual tile RTL generation with BEL instantiation - Switch matrix integration and port mapping - Configuration data routing and management - Supertile wrapper generation for hierarchical designs - Support for both VHDL and Verilog code generation - External I/O port handling and clock distribution

Classes#

Functions#

generateSuperTile(writer, fabric, superTile)[source]#
Parameters:
Return type:

None

Generate a super tile wrapper for given super tile.

Creates a hierarchical wrapper that instantiates multiple individual tiles and manages their interconnections. The supertile handles: - Internal tile-to-tile connections within the supertile - External port mapping to fabric-level connections - Configuration data distribution to sub-tiles - Clock signal routing and buffering - External I/O port aggregation

param writer:

The code generator instance for RTL output

type writer:

CodeGenerator

param fabric:

The fabric object containing global configuration

type fabric:

Fabric

param superTile:

Super tile object containing tile map and configuration

type superTile:

SuperTile

generateTile(writer, fabric, tile)[source]#
Parameters:
Return type:

None

Generate the RTL code for a tile given the tile object.

This function creates the complete RTL implementation for a tile, including: - Port declarations for all tile connections - BEL instantiations with proper port mapping - Switch matrix instantiation and connections - Configuration infrastructure (frame-based or FlipFlop chain) - Clock and reset signal distribution - Jump wire handling for long-distance connections

We first check if we need a configuration port. Currently we assume that each primitive needs a configuration port. However, a switch matrix can have no switch matrix multiplexers (e.g., when only bouncing back in border termination tiles)

TODO: we don’t do this and always create a configuration port for each tile. This dangle the CLK and MODE ports hanging in the air, which will throw a warning

Each switch matrix entity is build up is a specific order: 1.a) interconnect wire INPUTS (in the order defined by the fabric file,) 2.a) BEL primitive INPUTS (in the order the BEL-VHDLs are listed

in the fabric CSV) within each BEL, the order from the entity is maintained Note that INPUTS refers to the view of the switch matrix! Which corresponds to BEL outputs at the actual BEL

3.a) JUMP wire INPUTS (in the order defined by the fabric file) 1.b) interconnect wire OUTPUTS 2.b) BEL primitive OUTPUTS

Again: OUTPUTS refers to the view of the switch matrix which corresponds to

BEL inputs at the actual BEL

3.b) JUMP wire OUTPUTS The switch matrix uses single bit ports (std_logic and not std_logic_vector)!!!

param writer:

The code generator instance for RTL output

type writer:

CodeGenerator

param fabric:

The fabric object containing global configuration

type fabric:

Fabric

param tile:

The tile object containing BELs and port information

type tile:

Tile