FABulous.fabric_cad.gen_design_top_wrapper

User design top wrapper generation module.

This module provides functionality to generate top-level wrappers for user designs that interface with the FPGA fabric. The wrapper handles signal mapping between user logic and fabric I/O ports.

Classes

Functions

generateUserDesignTopWrapper(fabric, user_design_path, output)

Parameters:

• fabric (Fabric)

• user_design_path (Path)

• output (Path)

Return type:

None

Generate a top wrapper for the user design.

This function creates a Verilog top-level wrapper that instantiates the user’s design and connects its ports to the fabric’s external I/O BELs. It automatically discovers external ports from the fabric definition and generates the necessary wiring and BEL instantiations.

param fabric:

Fabric object

type fabric:

Fabric

param user_design_path:

Path to the user design file

type user_design_path:

Path

param output:

Path to output the user design top wrapper

type output:

Path

raises ValueError:

Output file is not a Verilog file or user design path is not a file