FABulous.fabric_definition.Bel#

Basic Element of Logic (BEL) definition module.

This module contains the Bel class which represents a Basic Element of Logic in the FPGA fabric. BELs are the fundamental building blocks that can be placed and configured within tiles, such as LUTs, flip-flops, and other logic elements.

Classes#

class Bel(src, prefix, module_name, internal, external, configPort, sharedPort, configBit, belMap, userCLK, ports_vectors, carry, localShared)[source]#

Information about a single BEL.

The information is parsed from the directory of the BEL in the CSV definition file. There are some things to be noted:

  • The parsed name will contain the prefix of the bel.

  • The sharedPort attribute is a list of Tuples with the name of the port and IO information, which is not expanded out yet.

  • If a port is marked as both shared and external, the port is considered as shared, as a result, signals like UserCLK will be in the shared port list, but not in the external port list.

Parameters:
src[source]#

The source directory of the BEL given in the CSV file.

Type:

Path

prefix[source]#

The prefix of the BEL given in the CSV file.

Type:

str

name[source]#

The name of the BEL, extracted from the source directory.

Type:

str

module_name[source]#

The name of the module in the bel. For verlog we can extract this from the RTL. For VHDL this is currently the same as name.

Type:

str

filetype[source]#

The file type of the BEL.

Type:

HDLType

inputs[source]#

All the normal input ports of the BEL.

Type:

list[str]

outputs[source]#

All the normal output ports of the BEL.

Type:

list[str]

externalInput[source]#

All the external input ports of the BEL.

Type:

list[str]

externalOutput[source]#

All the external output ports of the BEL.

Type:

list[str]

configPort[source]#

All the config ports of the BEL.

Type:

list[str]

sharedPort[source]#

All the shared ports of the BEL.

Type:

list[tuple[str, IO]]

configBit[source]#

The number of config bits of the BEL.

Type:

int

language[source]#

Language of the BEL. Currently only VHDL and Verilog are supported.

Type:

str

belFeatureMap[source]#

The feature map of the BEL.

Type:

dict[str, dict]

withUserCLK[source]#

Whether the BEL has userCLK port. Default is False.

Type:

bool

ports_vectors[source]#

Dict structure to save vectorized port information {<porttype>:{<portname>:(IO, <portwidth>)}}

Type:

dict[str, dict[str, tuple[IO, int]]]

carry[source]#

Carry chains by name. carry_name : {direction : port_name}

Type:

dict[str, dict[IO, str]]

localShared[source]#

{RESET/ENABLE,(portname, IO)} Local shared ports of the BEL. Are only shared in the Tile, not in the fabric.

Type:

dict[str,tuple[str, IO]]

Initialize a `Bel` object with the given parameters.

Methods: