FABulous.fabric_definition.Bel

Basic Element of Logic (BEL) definition module.

This module contains the Bel class which represents a Basic Element of Logic in the FPGA fabric. BELs are the fundamental building blocks that can be placed and configured within tiles, such as LUTs, flip-flops, and other logic elements.

Classes

class Bel(src, prefix, module_name, internal, external, configPort, sharedPort, configBit, belMap, userCLK, ports_vectors, carry, localShared)

Information about a single BEL.

The information is parsed from the directory of the BEL in the CSV definition file. There are some things to be noted:

• The parsed name will contain the prefix of the bel.

• The sharedPort attribute is a list of Tuples with the name of the port and IO information, which is not expanded out yet.

• If a port is marked as both shared and external, the port is considered as shared, as a result, signals like UserCLK will be in the shared port list, but not in the external port list.

Parameters:

• src (Path) – The source directory path of the BEL.

• prefix (str) – The prefix of the BEL.

• module_name (str) – The name of the module in the BEL.

• internal (list[tuple[str, IO]]) – List of internal ports with their IO direction.

• external (list[tuple[str, IO]]) – List of external ports with their IO direction.

• configPort (list[tuple[str, IO]]) – List of configuration ports with their IO direction.

• sharedPort (list[tuple[str, IO]]) – List of shared ports with their IO direction.

• configBit (int) – The number of configuration bits of the BEL.

• belMap (dict[str, dict]) – The feature map of the BEL.

• userCLK (bool) – Whether the BEL has userCLK port.

• ports_vectors (dict[str, dict[str, tuple[IO, int]]]) – Dictionary structure to save vectorized port information.

• carry (dict[str, dict[IO, str]]) – Carry chains by name.

• localShared (dict[str, tuple[str, IO]]) – Local shared ports of the BEL.

src

The source directory of the BEL given in the CSV file.

Type:

Path

prefix

The prefix of the BEL given in the CSV file.

Type:

str

name

The name of the BEL, extracted from the source directory.

Type:

str

module_name

The name of the module in the bel. For verlog we can extract this from the RTL. For VHDL this is currently the same as name.

Type:

str

filetype

The file type of the BEL.

Type:

HDLType

inputs

All the normal input ports of the BEL.

Type:

list[str]

outputs

All the normal output ports of the BEL.

Type:

list[str]

externalInput

All the external input ports of the BEL.

Type:

list[str]

externalOutput

All the external output ports of the BEL.

Type:

list[str]

configPort

All the config ports of the BEL.

Type:

list[tuple[str, IO]]

sharedPort

All the shared ports of the BEL.

Type:

list[tuple[str, IO]]

configBit

The number of config bits of the BEL.

Type:

int

language

Language of the BEL. Currently only VHDL and Verilog are supported.

Type:

str

belFeatureMap

The feature map of the BEL.

Type:

dict[str, dict]

withUserCLK

Whether the BEL has userCLK port. Default is False.

Type:

bool

ports_vectors

Dict structure to save vectorized port information {<porttype>:{<portname>:(IO, <portwidth>)}}

Type:

dict[str, dict[str, tuple[IO, int]]]

carry

Carry chains by name. carry_name : {direction : port_name}

Type:

dict[str, dict[IO, str]]

localShared

{RESET/ENABLE,(portname, IO)} Local shared ports of the BEL. Are only shared in the Tile, not in the fabric.

Type:

dict[str,tuple[str, IO]]

Raises:

ValueError – If the file type is not recognized (not .sv, .v, .vhd, or .vhdl).

Parameters:

• src (Path)

• prefix (str)

• module_name (str)

• internal (list[tuple[str, IO]])

• external (list[tuple[str, IO]])

• configPort (list[tuple[str, IO]])

• sharedPort (list[tuple[str, IO]])

• configBit (int)

• belMap (dict[str, dict])

• userCLK (bool)

• ports_vectors (dict[str, dict[str, tuple[IO, int]]])

• carry (dict[str, dict[IO, str]])

• localShared (dict[str, tuple[str, IO]])

Methods: