FABulous.geometry_generator.tile_geometry#

Tile geometry generation and management for FABulous FPGA tiles.

This module provides the TileGeometry class for representing and generating the geometric layout of FPGA tiles, including switch matrices, BELs, and interconnect wires. It handles both direct connections to neighboring tiles and complex stair-like routing for longer-distance connections.

Classes#

class TileGeometry[source]#

A data structure representing the geometry of a tile.

name[source]#

Name of the tile

Type:

str

width[source]#

Width of the tile

Type:

int

height[source]#

Height of the tile

Type:

int

border[source]#

Border of the fabric the tile is on

Type:

Border

smGeometry[source]#

Geometry of the tiles switch matrix

Type:

SmGeometry

belGeomList[source]#

List of the geometries of the tiles bels

Type:

List[BelGeometry]

wireGeomList[source]#

List of the geometries of the tiles wires

Type:

List[WireGeometry]

stairWiresList[source]#

List of the stair-like wires of the tile

Type:

List[StairWires]

Initialize a `TileGeometry` instance.
Initializes all attributes to default values
Type:

empty name, zero dimensions,

no border, and empty lists for geometric components.

Methods:

adjustDimensions(maxWidthInColumn, maxHeightInRow, maxSmWidthInColumn, maxSmRelXInColumn)[source]#

Adjust tile dimensions to match maximum values in fabric grid.

Normalizes the tile dimensions and switch matrix positioning to align with the maximum dimensions found in the same fabric column/row, ensuring uniform tile sizing across the fabric.

Parameters:

  • maxWidthInColumn (int) – Maximum width among tiles in the same column

  • maxHeightInRow (int) – Maximum height among tiles in the same row

  • maxSmWidthInColumn (int) – Maximum switch matrix width in the same column

  • maxSmRelXInColumn (int) – Maximum switch matrix relative X position in the same column

Return type:

None

adjustSmPos(lowestSmYInRow, padding)[source]#

Ajusts the position of the switch matrix.

This is done by using the lowest Y coordinate of any switch matrix in the same row for reference.

After this step is completed for all switch matrices, their southern edge will be on the same Y coordinate, allowing for easier inter-tile routing.

Parameters:

  • lowestSmYInRow (int)

  • padding (int)

Return type:

None

generateBelWires()[source]#

Generate the wires between the switch matrix and its bels.

Return type:

None

generateDirectWires(padding)[source]#

Generate wires to neigbouring tiles.

Parameters:

padding (int)

Return type:

None

generateGeometry(tile, padding)[source]#

Generate the geometry for a tile.

Creates geometric representations for all BELs and the switch matrix, then calculates the overall tile dimensions based on the generated components and padding requirements.

Parameters:

  • tile (Tile) – The Tile object to generate geometry for

  • padding (int) – The padding space to add around components

Return type:

None

generateIndirectWires(padding)[source]#

Generate wires to non-neighbouring tiles.

These wires require staircase-like routing patterns to reach tiles that are not direct neighbors (offset >= 2). The routing varies by tile side and wire direction.

Parameters:

padding (int) – The padding space to add around wire routing

Return type:

None

generateWires(padding)[source]#

Generate all wire geometries for the tile.

Creates wire geometries for BEL connections, direct connections to neighboring tiles, and indirect connections requiring stair-like routing. Ensures proper alignment of wire positions across different tile types.

Parameters:

padding (int) – The padding space to add around wire routing

Return type:

None

indirectEastSideWire(portGeom, padding)[source]#

Generate indirect wires on the east side of the tile with stair-like routing.

Creates staircase-shaped wire routing for connections that span multiple tiles eastward. Manages stair wire generation and space reservation based on wire direction and grouping.

Parameters:

  • portGeom (PortGeometry) – The port geometry defining the wire characteristics

  • padding (int) – The padding space around the wire routing

Return type:

None

indirectNorthSideWire(portGeom, padding)[source]#

Generate indirect wires with stair-like routing.

Creates staircase-shaped wire routing for connections that span multiple tiles northward. Manages stair wire generation and space reservation based on wire direction and grouping.

Parameters:

  • portGeom (PortGeometry) – The port geometry defining the wire characteristics

  • padding (int) – The padding space around the wire routing

Return type:

None

indirectSouthSideWire(portGeom)[source]#

Generate indirect wires on the south side without creating stair-like wires.

Creates L-shaped wire routing for southward connections. Unlike north side wires, this method only generates the connection wires and reserves space for stair wires created by the north side method.

Parameters:

portGeom (PortGeometry) – The port geometry defining the wire characteristics

Return type:

None

indirectWestSideWire(portGeom)[source]#

Generate indirect wires on the west side without creating stair-like wires.

Creates L-shaped wire routing for westward connections. Unlike east side wires, this method only generates the connection wires and reserves space for stair wires created by the east side method.

Parameters:

portGeom (PortGeometry) – The port geometry defining the wire characteristics

Return type:

None

saveToCSV(writer)[source]#

Save tile geometry data to CSV format.

Writes the tile geometry information including dimensions and all geometric components (switch matrix, BELs, wires, stair wires) to a CSV file using the provided writer.

Parameters:

writer (object) – The CSV writer object to use for output

Return type:

None

setBelPositions(padding)[source]#

Set BEL positions.

Parameters:

padding (int)

Return type:

None