FABulous.fabric_definition.Yosys_obj ==================================== .. py:module:: FABulous.fabric_definition.Yosys_obj .. autoapi-nested-parse:: Object representation of the Yosys Json file. Classes ------- .. py:class:: YosysCellDetails() Represents a cell instance in a Yosys module. Cells are instantiated components like logic gates, flip-flops, or user-defined modules. .. attribute:: hide_name Whether to hide the cell name in output (1=hide, 0=show). :type: {0, 1} .. attribute:: type Cell type/primitive name (e.g., "AND", "DFF", custom module name). :type: str .. attribute:: parameters Cell parameters as string key-value pairs. :type: dict[str, str] .. attribute:: attributes Cell attributes including metadata and synthesis directives. :type: dict[str, str | int] .. attribute:: connections Port connections mapping port names to bit vectors. :type: dict[str, BitVector] .. attribute:: port_directions Direction of each port. Default is empty dict. :type: dict[str, {"input", "output", "inout"}], optional .. attribute:: model Associated model name. Default is "". :type: str, optional .. py:class:: YosysJson(path) Root object representing a complete Yosys JSON file. This class provides the main interface for loading and analyzing Yosys JSON netlists. It contains all modules in the design and provides utility methods for common netlist analysis tasks. .. attribute:: srcPath Path to the source JSON file. :type: Path .. attribute:: creator Tool that created the JSON (usually "Yosys"). :type: str .. attribute:: modules Dictionary mapping module names to YosysModule objects. :type: dict[str, YosysModule] .. attribute:: models Dictionary of behavioral models (implementation-specific). :type: dict .. attribute:: Load and parse a HDL file to a Yosys JSON object. .. attribute:: :type: param path: Path to a HDL file. .. attribute:: :type: type path: Path .. attribute:: :type: raises FileNotFoundError: If the JSON file doesn't exist. .. attribute:: :type: raises json.JSONDecodeError: If the file contains invalid JSON. .. attribute:: :type: raises ValueError: If the HDL file type is unsupported. **Methods:** .. py:method:: getNetPortSrcSinks(net) Find the source and sink connections for a given net. This method analyzes the netlist to determine what drives a net (source) and what it connects to (sinks). :param net: Net ID to analyze. :type net: int :returns: A tuple containing: - Source: (cell_name, port_name) tuple for the driving cell/port - Sinks: List of (cell_name, port_name) tuples for driven cells/ports :rtype: tuple[tuple[str, str], list[tuple[str, str]]] :raises ValueError: If net is not found or has multiple drivers. .. rubric:: Notes If no driver is found, the source will be ("", "z") indicating a high-impedance or undriven net. .. py:method:: getTopModule() Find and return the top-level module in the design. The top module is identified by having a "top" attribute. :returns: A tuple containing: - The name of the top-level module (str) - The YosysModule object for the top-level module :rtype: tuple[str, YosysModule] :raises ValueError: If no top module is found in the design. .. py:method:: isTopModuleNet(net) Check if a net ID corresponds to a top-level module port. :param net: Net ID to check. :type net: int :returns: True if the net is connected to a top module port, False otherwise. :rtype: bool .. py:class:: YosysMemoryDetails() Represents memory block details in a Yosys module. Memory blocks are inferred or explicitly instantiated memory elements. .. attribute:: hide_name Whether to hide the memory name in output (1=hide, 0=show). :type: {0, 1} .. attribute:: attributes Memory attributes and metadata. :type: dict[str, str] .. attribute:: width Data width in bits. :type: int .. attribute:: start_offset Starting address offset. :type: int .. attribute:: size Memory size (number of addressable locations). :type: int .. py:class:: YosysModule(*, attributes, parameter_default_values, ports, cells, memories, netnames) Represents a module in a Yosys design. A module contains the structural description of a digital circuit including its interface (ports), internal components (cells), memory blocks, and interconnections (nets). .. attribute:: attributes Module attributes and metadata (e.g., "top" for top module). :type: dict[str, str | int] .. attribute:: parameter_default_values Default values for module parameters. :type: dict[str, str | int] .. attribute:: ports Dictionary mapping port names to YosysPortDetails. :type: dict[str, YosysPortDetails] .. attribute:: cells Dictionary mapping cell names to YosysCellDetails. :type: dict[str, YosysCellDetails] .. attribute:: memories Dictionary mapping memory names to YosysMemoryDetails. :type: dict[str, YosysMemoryDetails] .. attribute:: netnames Dictionary mapping net names to YosysNetDetails. :type: dict[str, YosysNetDetails] .. attribute:: Initialize a YosysModule from parsed JSON data. .. attribute:: :type: param attributes: Module attributes dictionary. .. attribute:: :type: type attributes: dict .. attribute:: :type: param parameter_default_values: Parameter defaults dictionary. .. attribute:: :type: type parameter_default_values: dict .. attribute:: :type: param ports: Ports dictionary (will be converted to YosysPortDetails objects). .. attribute:: :type: type ports: dict .. attribute:: :type: param cells: Cells dictionary (will be converted to YosysCellDetails objects). .. attribute:: :type: type cells: dict .. attribute:: :type: param memories: Memories dictionary (will be converted to YosysMemoryDetails objects). .. attribute:: :type: type memories: dict .. attribute:: :type: param netnames: Netnames dictionary (will be converted to YosysNetDetails objects). .. attribute:: :type: type netnames: dict **Methods:** .. py:class:: YosysNetDetails() Represents net/wire details in a Yosys module. Nets are the connections between cells and ports in the design. .. attribute:: hide_name Whether to hide the net name in output (1=hide, 0=show). :type: {0, 1} .. attribute:: bits Bit vector representing the net's signals. :type: BitVector .. attribute:: attributes Net attributes including unused bit information. :type: dict[str, str] .. attribute:: offset Bit offset for multi-bit nets. :type: int, default 0 .. attribute:: upto Upper bound for bit ranges. :type: int, default 0 .. attribute:: signed Whether the net is signed (0=unsigned, 1=signed). :type: int, default 0 .. py:class:: YosysPortDetails() Represents port details in a Yosys module. .. attribute:: direction Port direction. :type: {"input", "output", "inout"} .. attribute:: bits Bit vector representing the port's signals. :type: BitVector .. attribute:: offset Bit offset for multi-bit ports. :type: int, default 0 .. attribute:: upto Upper bound for bit ranges. :type: int, default 0 .. attribute:: signed Whether the port is signed (0=unsigned, 1=signed). :type: int, default 0 Functions --------- Module Attributes ----------------- .. py:data:: BitVector :no-index: .. py:data:: KeyValue :no-index: