FABulous.FABulous_CLI.cmd_synthesis

Synthesis command implementation for the FABulous CLI.

This module provides the synthesis command functionality for the FABulous command-line interface. It implements Yosys-based FPGA synthesis targeting the nextpnr place-and- route tool, with support for various synthesis options and output formats.

The synthesis flow includes multiple stages, from reading the Verilog files through final netlist generation, with options for LUT mapping, FSM optimization, carry chain mapping, and memory inference.

Functions

do_synthesis(self, args)

Parameters:

• self (FABulous_CLI)

• args (Namespace)

Return type:

None

Run Yosys synthesis for the specified Verilog files.

Performs FPGA synthesis using Yosys with the nextpnr JSON backend to synthesize Verilog designs and generate nextpnr-compatible JSON files for place and route. It supports various synthesis options including LUT architecture, FSM optimization, carry mapping, and different output formats.

param self:

The CLI instance containing project and fabric information.

type self:

FABulous_CLI

param args:

Command arguments containing: - files: List of Verilog files to synthesize - top: Top module name (default: ‘top_wrapper’) - auto_top: Whether to automatically determine top module - json: Output JSON file path - blif: Output BLIF file path (optional) - edif: Output EDIF file path (optional) - lut: LUT architecture size (default: 4) - And various other synthesis options

type args:

argparse.Namespace

Notes

The synthesis process includes multiple stages: hierarchy checking, flattening, coarse synthesis, RAM mapping, gate mapping, FF mapping, LUT mapping, and final netlist generation. See the module docstring for detailed synthesis flow information.

Module Attributes

CMD_USER_DESIGN_FLOW

HELP

synthesis_parser