FABulous.fabric_definition.SuperTile

Supertile definition for FPGA fabric.

This module contains the SuperTile class, which represents a composite tile made up of multiple smaller, individual tiles. Supertiles allow for the creation of more larger, complex and hierarchical structures within the FPGA fabric, combining different functionalities into a single, reusable block.

Classes

class SuperTile

Store the information about a super tile.

name

The name of the super tile

Type:

str

tiles

The list of tiles that make up the super tile

Type:

list[Tile]

tileMap

The map of the tiles that make up the super tile

Type:

list[list[Tile]]

bels

The list of bels of that the super tile contains

Type:

list[Bel]

withUserCLK

Whether the super tile has a userCLK port. Default is False.

Type:

bool

Methods:

getInternalConnections()

Return all the internal connections of the supertile.

Returns:

list – A list of tuples which contains the internal connected port and the x and y coordinate of the tile.

Return type:

[tuple[list[Port], int, int]]

getPortsAroundTile()

Return all the ports that are around the supertile.

The dictionary key is the location of where the tile is located in the supertile map with the format of “X{x}Y{y}”, where x is the x coordinate of the tile and y is the y coordinate of the tile. The top left tile will have key “00”.

Returns:

dict – The dictionary of the ports around the super tile.

Return type:

[str, list[list[Port]]]