FABulous.fabric_definition.Bel
==============================

.. py:module:: FABulous.fabric_definition.Bel

.. autoapi-nested-parse::
   Basic Element of Logic (BEL) definition module.

   This module contains the `Bel` class which represents a Basic Element of Logic in the
   FPGA fabric.
   BELs are the fundamental building blocks that can be placed and configured within tiles,
   such as LUTs, flip-flops, and other logic elements.



Classes
-------

.. py:class:: Bel(src, prefix, module_name, internal, external, configPort, sharedPort, configBit, belMap, userCLK, ports_vectors, carry, localShared)

   Information about a single BEL.

   The information is parsed from the directory of the BEL in the CSV definition file.
   There are some things to be noted:

   - The parsed name will contain the prefix of the bel.
   - The `sharedPort` attribute is a list of Tuples with the name of the port and
     IO information, which is not expanded out yet.
   - If a port is marked as both shared and external, the port is considered as shared,
     as a result, signals like UserCLK will be in the shared port list,
     but not in the external port list.

   .. attribute:: src

      The source directory of the BEL given in the CSV file.

      :type: pathlib.Path

   .. attribute:: prefix

      The prefix of the BEL given in the CSV file.

      :type: str

   .. attribute:: name

      The name of the BEL, extracted from the source directory.

      :type: str

   .. attribute:: module_name

      The name of the module in the bel.
      For verlog we can extract this from the RTL.
      For VHDL this is currently the same as name.

      :type: str

   .. attribute:: filetype

      The file type of the BEL.

      :type: HDLType

   .. attribute:: inputs

      All the normal input ports of the BEL.

      :type: list[str]

   .. attribute:: outputs

      All the normal output ports of the BEL.

      :type: list[str]

   .. attribute:: externalInput

      All the external input ports of the BEL.

      :type: list[str]

   .. attribute:: externalOutput

      All the external output ports of the BEL.

      :type: list[str]

   .. attribute:: configPort

      All the config ports of the BEL.

      :type: list[str]

   .. attribute:: sharedPort

      All the shared ports of the BEL.

      :type: list[tuple[str, IO]]

   .. attribute:: configBit

      The number of config bits of the BEL.

      :type: int

   .. attribute:: language

      Language of the BEL. Currently only VHDL and Verilog are supported.

      :type: str

   .. attribute:: belFeatureMap

      The feature map of the BEL.

      :type: dict[str, dict]

   .. attribute:: withUserCLK

      Whether the BEL has userCLK port. Default is False.

      :type: bool

   .. attribute:: ports_vectors

      Dict structure to save vectorized port information
      {<porttype>:{<portname>:(IO, <portwidth>)}}

      :type: dict[str, dict[str, tuple[IO, int]]]

   .. attribute:: carry

      Carry chains by name.
      carry_name : {direction : port_name}

      :type: dict[str, dict[IO, str]]

   .. attribute:: localShared

      {RESET/ENABLE,(portname, IO)}
      Local shared ports of the BEL.
      Are only shared in the Tile, not in the fabric.

      :type: dict[str,tuple[str, IO]]

   .. attribute:: Initialize a `Bel` object with the given parameters.

      

   .. attribute:: 

      

      :type: param src: The source directory path of the BEL.

   .. attribute:: 

      

      :type: type src: pathlib.Path

   .. attribute:: 

      

      :type: param prefix: The prefix of the BEL.

   .. attribute:: 

      

      :type: type prefix: str

   .. attribute:: 

      

      :type: param module_name: The name of the module in the BEL.

   .. attribute:: 

      

      :type: type module_name: str

   .. attribute:: 

      

      :type: param filetype: The file type of the BEL.

   .. attribute:: 

      

      :type: type filetype: str

   .. attribute:: 

      

      :type: param internal: List of internal ports with their IO direction.

   .. attribute:: 

      

      :type: type internal: list[tuple[str, IO]]

   .. attribute:: 

      

      :type: param external: List of external ports with their IO direction.

   .. attribute:: 

      

      :type: type external: list[tuple[str, IO]]

   .. attribute:: 

      

      :type: param configPort: List of configuration ports with their IO direction.

   .. attribute:: 

      

      :type: type configPort: list[tuple[str, IO]]

   .. attribute:: 

      

      :type: param sharedPort: List of shared ports with their IO direction.

   .. attribute:: 

      

      :type: type sharedPort: list[tuple[str, IO]]

   .. attribute:: 

      

      :type: param configBit: The number of configuration bits of the BEL.

   .. attribute:: 

      

      :type: type configBit: int

   .. attribute:: 

      

      :type: param belMap: The feature map of the BEL.

   .. attribute:: 

      

      :type: type belMap: dict[str, dict]

   .. attribute:: 

      

      :type: param userCLK: Whether the BEL has userCLK port.

   .. attribute:: 

      

      :type: type userCLK: bool

   .. attribute:: 

      

      :type: param individually_declared: Whether ports are individually declared.

   .. attribute:: 

      

      :type: type individually_declared: bool

   .. attribute:: 

      

      :type: param ports_vectors: Dictionary structure to save vectorized port information.

   .. attribute:: 

      

      :type: type ports_vectors: dict[str, dict[str, tuple[IO, int]]]

   .. attribute:: 

      

      :type: param carry: Carry chains by name.

   .. attribute:: 

      

      :type: type carry: dict[str, dict[IO, str]]

   .. attribute:: 

      

      :type: param localShared: Local shared ports of the BEL.

   .. attribute:: 

      

      :type: type localShared: dict[str, tuple[str, IO]]

   .. attribute:: 

      

      :type: raises ValueError: If the file type is not recognized (not .sv, .v, .vhd, or .vhdl).



   **Methods:**