FABulous.fabric_definition.Port =============================== .. py:module:: FABulous.fabric_definition.Port .. autoapi-nested-parse:: Port definition module for FPGA fabric. This module contains the `Port` class, which represents a connection point on a tile in the FPGA fabric. Ports define the physical and logical characteristics of wires entering or leaving a tile, including their direction, source and destination names, offsets, and wire counts. These definitions are typically parsed from a CSV file that describes the fabric architecture. Classes ------- .. py:class:: Port() Store all the port information defined in the CSV file. The `name`, `inOut` and `sideOfTile` are added attributes to aid the generation of the fabric. The `name` and `inOut` are related. If the `inOut` is `INPUT`, then the name is the source name of the port on the tile. Otherwise, the name is the destination name of the port on the tile. The `sideOfTile` defines where the port is physically located on the tile, since for a north direction wire, the input will be physically located on the south side of the tile. The `sideOfTile` will make determining where the port is located much easier. .. attribute:: wireDirection The direction attribute in the CSV file :type: Direction .. attribute:: sourceName The source_name attribute in the CSV file :type: str .. attribute:: xOffset The X-offset attribute in the CSV file :type: int .. attribute:: yOffset The Y-offset attribute in the CSV file :type: int .. attribute:: destinationName The destination_name attribute in the CSV file :type: str .. attribute:: wireCount The wires attribute in the CSV file :type: int .. attribute:: name The name of the port :type: str .. attribute:: inOut The IO direction of the port :type: IO .. attribute:: sideOfTile The side on which the port is physically located in the tile :type: Side **Methods:** .. py:method:: expandPortInfo(mode = 'SwitchMatrix') Expand the port information to the individual bit signal. If 'Indexed' is in the mode, then brackets are added to the signal name. :param mode: Mode for expansion. Defaults to "SwitchMatrix". Possible modes are 'all', 'allIndexed', 'Top', 'TopIndexed', 'AutoTop', 'AutoTopIndexed', 'SwitchMatrix', 'SwitchMatrixIndexed', 'AutoSwitchMatrix', 'AutoSwitchMatrixIndexed' :type mode: str, optional :returns: **Tuple** -- A tuple of two lists. The first list contains the source names of the ports and the second list contains the destination names of the ports. :rtype: [list[str], list[str]] .. py:method:: expandPortInfoByName(indexed = False) Expand port information to individual wire names. Generates a list of individual wire names for this port, accounting for wire count and offset calculations. For termination ports (NULL), the wire count is multiplied by the Manhattan distance. :param indexed: If True, wire names use bracket notation (e.g., `port[0]`). If False, wire names use simple concatenation (e.g., `port0`). Defaults to False. :type indexed: bool, optional :returns: List of individual wire names for this port. :rtype: list[str] .. py:method:: expandPortInfoByNameTop(indexed = False) Expand port information for top-level connections. Similar to expandPortInfoByName but specifically for top-level tile connections. The start index is calculated differently to handle the top slice of wires for routing fabric connections. :param indexed: If True, wire names use bracket notation (e.g., `port[0]`). If False, wire names use simple concatenation (e.g., `port0`). Defaults to False. :type indexed: bool, optional :returns: List of individual wire names for top-level connections. :rtype: list[str]